1. Technical Field
The present disclosure relates to the field of voltage controlled oscillators. The present disclosure relates more particularly to the field of ring oscillators.
2. Description of the Related Art
Phase locked loops are commonly used in integrated circuits to ensure that clock signals used throughout the integrated circuit die have phases that are locked together. Phase locked loops typically include a voltage controlled oscillator (VCO) that generates an oscillator signal having a particular frequency. Typically, the phase locked loop also includes an input oscillator signal. The phase locked loop ensures that the phase of the input oscillator signal and the phase of the oscillator signal generated by the VCO are locked together in a particular relationship.
To assist in this, the phase locked loop typically includes a frequency divider that divides the oscillator signal by some integer number. The frequency divider is in the feedback path of the phase locked loop and it divides the voltage controlled oscillator output. The divided oscillator signal is fed back to a phase detector. The input oscillator signal is also provided to the phase detector. The phase detector outputs a phase difference signal indicative of a phase difference between the divided oscillator signal and the input oscillator signal. The phase difference signal is fed back to the voltage controlled oscillator with the fact that the output oscillator signal of the VCO has a phase that is locked with the phase of the input oscillator signal.
With state-of-the art phase-locked loops outputting frequencies in the multi-GHz frequency range, power optimization is a key goal to increase the battery life. Reducing the power consumption of the divider is beneficial in realizing low-power PLL.
However, standard frequency dividers consume large amounts of power. In particular, at RF frequencies the power consumed by the frequency divider is a substantial portion of the total phase locked loop power consumption. It is desirable to provide a phase locked loop with reduced power consumption.